Ultra Low Power Digital Logic Circuits in Sub-threshold for Biomedical Applications

Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits, by operating the devices at low currents and low voltages[1,2,3,4].It is known that MOS devices and circuits especially CMOS circuits consume relatively low power[5,6] . But there seems to be a need to reduce this power further to prolong the life of battery. One solution to achieve the ultra-power requirement is to operate in sub-threshold region [7]. Over the last 10 years, digital sub-threshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the priority. Sub-threshold logic transistors, that is the power supply voltage is below the threshold voltage. In this paper, analysis was done both CMOS and Pseudo-NMOS logic families operating in subthreshold region. The results were compared with CMOS in normal strong inversion region.